class

GB::Memory

Inherits Reference < Object

Constants

ECHO = 57344..65023
EXTERNAL_RAM = 40960..49151
HRAM = 65408..65534
INTERRUPT_REG = 65535
IO_PORTS = 65280..65407
NOT_USABLE = 65184..65279
OAM = 65024..65183
ROM_BANK_0 = 0..16383
ROM_BANK_N = 16384..32767
VRAM = 32768..40959
WORK_RAM_0 = 49152..53247
WORK_RAM_N = 53248..57343

Constructors

new(gb : GB)
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Instance methods

[](index : Int) : UInt8

read 8 bits from memory and tick other components

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[]=(index : Int, value : UInt8) : Nil

write 8 bits to memory and tick other components

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[]=(index : Int, value : UInt16) : Nil

write 16 bits to memory

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bootrom
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bootrom=(bootrom : Slice(UInt8))
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dma_tick(cycles : Int) : Nil

DMA should start 8 T-cycles after a write to 0xFF46. That's what @requested_oam_dma_transfer and @next_dma_counter are for. After that, memory is still blocked for an additional 4 T-cycles, which is why I increment @dma_position past 0xA0, even though it only transfers 0xA0 bytes. I just use it as an indicator of when memory should unlock again. Note: According to a comment in gekkio's oam_dma_start test, if DMA is restarted while it has not yet completed, the 8 T-cycles should be spent continuing the first DMA rather than jumping to the new one.

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dma_transfer(source : UInt8) : Nil
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read_byte(index : Int) : UInt8

read 8 bits from memory (doesn't tick components)

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read_word(index : Int) : UInt16

read 16 bits from memory

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reset_cycle_count
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skip_boot
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stop_instr
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tick_components(cycles = 4, from_cpu = true, ignore_speed = false) : Nil

keep other components in sync with memory, usually before memory access

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tick_extra(total_expected_cycles : Int) : Nil

tick remainder of expected cycles, then reset counter

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write_byte(index : Int, value : UInt8) : Nil

write a 8 bits to memory (doesn't tick components)

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