class

Swanium::Core::WonderSwanBus

Inherits Swanium::Core::MemoryBus < Reference < Object

Platform-neutral first hardware bus. It models the CPU-visible address map and cartridge bank registers while PPU/APU/DMA devices are added on top through the same I/O port file.

Constants

OPEN_BUS = 255_u8

Constructors

from_cartridge(cartridge : CartridgeImage) : WonderSwanBus
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new(rom : Bytes = Bytes.new(0), save_ram_size : Int = 0, model : WonderSwanModel = WonderSwanModel::Mono, cartridge_header : CartridgeHeader | Nil = nil, save_ram_mapped : Bool = true)
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Instance methods

capture_next_frame_sprites(ppu : Ppu) : Nil
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cartridge_header
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consume_voice_writes

Drains the voice writes collected during the preceding CPU instruction. This runs at every instruction boundary, so retain the backing storage instead of replacing it with a newly allocated Array each time.

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consume_wait_cycles

Some hardware I/O operations synchronously stall the V30. A bus accumulates those costs while handling an instruction, and the CPU consumes them before reporting that instruction's total cycle count.

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has_rtc?
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has_save_ram?
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interrupt_pending?(source : WonderSwanInterrupt) : Bool
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keys
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latch_sprites(ppu : Ppu) : Nil

PPU access stays behind the bus boundary: the renderer receives the internal views it requires, while frontends never receive mutable RAM or port-file references.

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linear_offset
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load_dma_state(io : IO) : Nil
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load_rtc_state(io : IO) : Nil
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model
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on_hblank

Called by the LCD scheduler at the beginning of HBlank.

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on_vblank

Called by the LCD scheduler on the VBlank transition.

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pending_interrupt_vector?
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ports_size
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ports_snapshot
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ram_bank
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ram_bank_hi
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read_io(port : UInt8) : UInt8

Default open-bus I/O behavior keeps FlatMemory suitable for CPU specs.

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read_u8(address : UInt32) : UInt8
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render_scanline(ppu : Ppu, line : UInt8) : Nil
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replace_save_ram(data : Bytes) : Nil
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request_interrupt(source : WonderSwanInterrupt) : Nil
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restore_state(work_ram : Bytes, save_ram : Bytes, ports : Bytes, keys : UInt16, linear_offset : UInt8, ram_bank : UInt8, ram_bank_hi : UInt8, rom_bank0 : UInt8, rom_bank0_hi : UInt8, rom_bank1 : UInt8, rom_bank1_hi : UInt8) : Nil
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rom_bank0
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rom_bank0_hi
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rom_bank1
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rom_bank1_hi
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save_dma_state(io : IO) : Nil
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save_ram_size
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save_ram_snapshot
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save_rtc_state(io : IO) : Nil
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set_current_scanline(line : UInt8) : Nil

The display controller updates this once per 256-cycle scanline.

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set_keys(keys : UInt16) : Nil

The platform layer supplies a complete input snapshot. Only a newly pressed key raises the edge-triggered KeyPress source.

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set_rtc_datetime(year : UInt8, month : UInt8, day : UInt8, weekday : UInt8, hour : UInt8, minute : UInt8, second : UInt8) : Nil
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tick_rtc(cycles : UInt32) : Nil
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tick_sound(cycles : UInt32, apu : Apu) : Nil
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work_ram_size
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work_ram_snapshot

Snapshot methods intentionally return independent buffers. Hardware state must otherwise be mutated through the address or I/O maps so device-specific masks and side effects cannot be bypassed.

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write_io(port : UInt8, value : UInt8) : Nil
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write_u8(address : UInt32, value : UInt8) : Nil
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