class

Swanium::Core::Machine

Inherits Reference < Object

Platform-independent owner for emulation state. Hardware components will be added here without exposing SDL, filesystem, or wall-clock dependencies.

Constants

CYCLES_PER_FRAME = CYCLES_PER_SCANLINE.to_u64 * SCANLINES_PER_FRAME
CYCLES_PER_SCANLINE = 256_u32
SCANLINES_PER_FRAME = 159_u16
VISIBLE_SCANLINES = 144_u16

Constructors

Instance methods

cycles
Source
framebuffer_rgba
Source
restore_timing(cycles : UInt64, scanline : UInt16, scanline_cycles : UInt32) : Nil
Source
run_wonder_swan_frame(bus : WonderSwanBus, keys : UInt16 = 0_u16) : Nil

Advance to the next fixed 159-line WonderSwan frame deadline with one stable input snapshot. This is deliberately driven from emulated cycles rather than wall-clock time, so headless test ROMs observe the same input and timer schedule as a frontend would. A CPU instruction is indivisible and can cross a deadline; the following deadline remains anchored to the master clock so that crossing does not accumulate drift.

Source
scanline
Source
scanline_cycles
Source
step(bus : WonderSwanBus) : UInt32

Run one CPU instruction and acknowledge the WonderSwan bus's highest-priority enabled request at the following instruction boundary.

Source