Memory
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DMA should start 8 T-cycles after a write to 0xFF46. That's what
@requested_oam_dma_transfer and @next_dma_counter are for. After that,
memory is still blocked for an additional 4 T-cycles, which is why I
increment @dma_position past 0xA0, even though it only transfers 0xA0
bytes. I just use it as an indicator of when memory should unlock again.
Note: According to a comment in gekkio's oam_dma_start test, if DMA is
restarted while it has not yet completed, the 8 T-cycles should
be spent continuing the first DMA rather than jumping to the new one.
keep other components in sync with memory, usually before memory access
tick remainder of expected cycles, then reset counter
write a 8 bits to memory (doesn't tick components)