CPU
Inherits Reference < Object
Constants
ADD = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::BI, (MC::EO | MC::AI) | MC::FI]
ADI = StaticArray[F1, F2, MC::IO | MC::BI, (MC::EO | MC::AI) | MC::FI, MC::None]
CMP = StaticArray[F1, F2, MC::IO | MC::MI, ((MC::RO | MC::BI) | MC::SU) | MC::FI, MC::None]
F1 = MC::CO | MC::MI
Fetch instruction microcode
F2 = (MC::RO | MC::II) | MC::CE
HLT = StaticArray[F1, F2, MC::HLT, MC::None, MC::None]
JC = StaticArray[F1, F2, MC::IO | MC::JC, MC::None, MC::None]
JMP = StaticArray[F1, F2, MC::IO | MC::J, MC::None, MC::None]
JPA = StaticArray[F1, F2, MC::AO | MC::J, MC::None, MC::None]
JZ = StaticArray[F1, F2, MC::IO | MC::JZ, MC::None, MC::None]
LABEL_REGEX = /^(?<label>[a-z\_\d]+)\:/i
LDA = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::AI, MC::None]
LDI = StaticArray[F1, F2, MC::IO | MC::AI, MC::None, MC::None]
LSR = StaticArray[F1, F2, MC::SR | MC::FI, MC::None, MC::None]
NOP = StaticArray[F1, F2, MC::None, MC::None, MC::None]
Opcodes
OUT = StaticArray[F1, F2, MC::AO | MC::OI, MC::None, MC::None]
ROM = Slice[NOP, LDA, ADD, SUB, STA, LDI, JMP, JC, JZ, ADI, JPA, CMP, LSR, SBI, OUT, HLT]
Set opcodes in micro-code ROM
SBI = StaticArray[F1, F2, MC::IO | MC::BI, ((MC::EO | MC::SU) | MC::AI) | MC::FI, MC::None]
STA = StaticArray[F1, F2, MC::IO | MC::MI, MC::AO | MC::RI, MC::None]
SUB = StaticArray[F1, F2, MC::IO | MC::MI, MC::RO | MC::BI, ((MC::EO | MC::AI) | MC::SU) | MC::FI]
SYM_REGEX = /\:(?<label>[a-z\_\d]+)/i
Constructors
Class methods
Instance methods
address
Sourceaddress=(address : UInt8)
Sourcebus
Sourcebus_receive
Sourcecontrol
Sourcemc_step
Sourceoptions
Sourceoptions=(options : Options)
Sourceprint_state
Sourceprogram_counter
Sourceram
Sourceram=(ram : Bytes)
Sourcereg_a
Sourcereg_b
Sourcereg_f
Sourcereg_i
Sourcereg_o
Sourcerun
Sourcestep
Source